(a) Field of the Invention
The present invention relates to a technology for forming an optical waveguide integral with an electric wiring board. More specifically, it relates to a method of manufacturing an optical waveguide laminated wiring board including a wiring board and an optical waveguide laminated thereon, the optical waveguide laminated wiring board being used for surface mounting an optical component such as a light emitting element and a light receiving element.
Since such an optical waveguide laminated wiring board plays a role in mounting of an electronic component such as a semiconductor element besides an optical component, the optical waveguide laminated wiring board is also referred to as a “package” for convenience in the description below.
(b) Description of the Related Art
There are various structures as a form of a wiring board integral with an optical waveguide. In one of such structures, an optical waveguide (a structure including a core layer for transmitting an optical signal, and cladding layers laminated on and below the core layer in a sandwiching manner) is laminated on a surface layer or an inner layer of a board used as a package or the like. An electronic component such as a semiconductor element (IC chip) in addition to an optical component such as a laser element is mounted on the surface of the wiring board having the above-described structure. Accordingly, a conductive via penetrating an optical waveguide in a thickness direction thereof has to be formed as means for electrically connecting an electrode terminal of each component to a pad for connection (a portion defined at a desired position in a wiring layer on the surface layer or in the inner layer) provided in the wiring board.
For example, for a structure where an optical waveguide is laminated on a surface layer of a wiring board, a method typically adopted to form a conductive via in the optical waveguide is as follows. Specifically, a via hole is formed at a desired position in the optical waveguide by a laser or the like, the via hole reaching a pad of the board. Then, the via hole is filled with a conductive material by electroless plating, or the like.
An example of a technique related to the above-mentioned prior art is described in Japanese unexamined Patent Publication (Kokai) 2002-250830. This document discloses an IC chip mounting board including: a conductor circuit and an interlayer resin insulating layer laminated on each of surfaces of a substrate; a solder resist layer formed on the outermost layer; and an optical element mounted on the IC chip mounting board. Moreover, an optical waveguide is formed within the board, and an optical signal transmitting optical path is formed to connect the optical element to the optical waveguide.
In a conventional wiring board integral with an optical waveguide as described above, as means for connecting an electrode terminal of an optical component or the like mounted on the surface of the wiring board to a pad of the wiring board, a conductive via is provided in the optical waveguide. As a method of forming the conductive via, a via hole opened in the optical waveguide is filled with a conductive material (Cu or the like) by copper (Cu) electroless plating, or the like. Specifically, after the optical waveguide (including a core layer and cladding layers laminated on and below the core layer in a sandwiching manner) is completed, the forming and then filling of the via hole are performed.
For this reason, a restriction is imposed by the aspect ratio (ratio of the diameter of the via to the thickness of the board) and the depth of the via, such that such conductive vias cannot be arranged at smaller intervals (at fine pitches). Incidentally, when a vertical-cavity surface-emitting laser (VCSEL) is mounted as the optical component, the pitch of the vias is desirably approximately 125 μm or approximately 62.5 μm. It is difficult to meet such a demand with the aforementioned conventional method of forming a conductive via. Namely, the conventional technique has a difficulty in arranging conductive vias at fine pitches.
Moreover, the restriction by the aspect ratio and the via depth brings about the following problem. When the aspect ratio is 1 or lower (for example, the via diameter is 50 μm while the thickness of the optical waveguide is 55 μm), it is highly likely that a conductive material is insufficiently filled into the via hole thus opened (for example, filling by Cu plating). In this case, since the conductive material is not filled sufficiently, an electrical conduction failure is caused between an electrode terminal of a component to be mounted and a pad of a board, which are connected to each other through the conductive via (the connection reliability is impaired). Consequently, the yield rate is reduced.